P-n junctions and, more generally, doping technology, play a quintessential role in semiconductor manufacturing. Forming a p-n junction oftentimes is achieved by doping a semiconductor with a suitable impurity; that is, intentionally introducing an impurity into an otherwise ultra-pure (intrinsic) semiconductor. Sometimes, an n-i or p-i junction is formed instead of a p-n junction (i meaning “intrinsic”), for use in specialized devices, such as detectors. The role of doping in semiconductor devices is to alter the electrical properties of the intrinsic semiconductor material in a predetermined fashion, so as to achieve a particular functional device, such as a transistor.
There has been a steady stream of improvements to the doping process by means of introducing gaseous dopants into a diffusion furnace with precise temperature control. One such example is presented in U.S. Pat. No. 3,660,179 which utilizes a counter-flow of an inert gas within a diffusion furnace, with this flow then improving the uniformity of dopant concentration along the length of the diffusion carrier.
Today's common thermal diffusion practice relies on splitting the doping process into two parts. First, the requisite dopant materials are introduced onto a semiconductor wafer in a pre-deposition step. The dopant source may be in solid, liquid or gaseous form. Many different processes are well-known in the prior art for delivering the dopant atoms to the semiconductor wafer surface. The system temperature at this step is relatively low, so the dopants are predominantly located at or near the surface of the wafer. Next, a higher temperature process is employed (referred to as a “drive-in” process) to cause the dopants to diffuse further into the wafer (thermal diffusion). During the drive-in process, it is clear that only the dopants deposited during the first step are available to participate in the diffusion step—any dopant materials remaining in the diffusion furnace are lost to further processing. The selected higher temperature and the time length of the drive-in process will determine the final diffusion profile (i.e., the spatial distribution of the dopant in the semiconductor wafer).
There is one extremely important feature of thermal diffusion: as a result of thermodynamic considerations, all of the dopant atoms are become diffused into the bulk semiconductor wafer are located at substitutional sites. That is, all of the dopant atoms are electrically active and the dopant efficiency is 100%.
With the advent of semiconductor lithography, all semiconductors have shrunk in size. This reduction in size necessitated concomitant reductions in spacing between different regions of an exemplary device, including, for example, a reduction in p-n junction depth. It was thereafter discovered that a thermal diffusion process was not able to create shallow p-n junctions with a well-controlled dopant profile for smaller devices. The industry then switched to ion implantation as a preferred alternative for doping semiconductor material.
U.S. Pat. No. 3,341,754 discloses an exemplary ion implantation system, where a method of producing precision resistors with ions capable of moving into substitutional positions under the influence of heat is described. During ion implantation, ionized dopant atom ions are accelerated in an electric field to an energy sufficient to penetrate into a semiconductor wafer's bulk. When accelerated dopant atoms enter the semiconductor, they experience collisions and columbic interactions with the semiconductor's nuclei and electrons, transferring their momentum and energy until they come to a complete stop.
Depending on the energy and mass of an impinging ion, the semiconductor's crystal structure can be damaged (or even destroyed) by the energetic collisions. This situation necessitates the utilization of a post-implantation annealing step. During the anneal, the temperature of the semiconductor is raised to a high temperature for a period of time sufficient to move implanted dopant atoms from their initial interstitial positions into substitutional positions, thus making the dopant electrically active. As a consequence of the non-equilibrium nature of the ion implantation process, not all of the post-anneal implanted dopants will move into substitutional sites. Thus, dopant efficiency of the ion implantation process is always less than 100%. In fact, the dopant atoms that remain in interstitial positions create permanent residual damage, negatively impacting the resulting semiconductor device performance in terms of carrier mobility, increased junction leakage and reduced breakdown voltage.
Even in light of these problems, ion implantation-based doping remained as a mainstay of the semiconductor industry for several decades, until the continued device scaling reduced the gate length of MOS devices to a value less than 100 nm. Currently, random dopant fluctuation (RDF), related to ion implantation variances, remains problematic. In MOSFET devices, RDF in the channel region can alter the transistor's properties, especially in newer process technologies since the total number of dopants is fewer. Thus, the addition or deletion of just a few impurity atoms can significantly alter transistor properties. RDF is a local form of process variation, meaning that two juxtaposed transistors may have significantly different dopant concentrations.
As will be discussed below, the present invention will address this problem with using a rapid thermal epitaxy (RTE) process. In order to understand the various processes developed over time, as well as their relation to the subject matter of the present invention, selected ones of the processes will first be described, starting with chemical vapor deposition (CVD), which is the most generic term used in the field of integrated circuit fabrication.
CVD is a chemical process used to produce solid materials—in most cases, thin films on formed on various substrates. In a typical CVD process, the substrate is exposed to volatile precursors, which react and/or decompose on the substrate surface to produce the desired film. Volatile by-products are also produced, which are removed by gas flow through the reaction chamber.
Epitaxy, a variant of the CVD process, is commonly defined as a deposition of a crystalline film on a crystalline substrate, where the film forms in registration with the crystallographic orientation of the substrate. The term epitaxy comes from the Greek roots epi, which means “above”, and taxis, which means “in an ordered manner”. The term “epitaxy” can also be translated to mean “to arrange upon”. As used in the case of semiconductor processing, an epitaxial film will form only a single, well-defined orientation with respect to the substrate crystal structure (single-domain epitaxy).
Epitaxial films can be grown from gaseous or liquid precursors. Since the substrate act as a “seed” crystal, the deposited film will lock into one or more of the crystallographic orientations of the substrate crystal. If an epitaxial film is deposited on a substrate of the same composition, the process is defined as “homo-epitaxy”, otherwise, it referred to as “hetero-epitaxy”. Traditional epitaxial processes tend to have high growth rates, and can approach 1 μm/min or more.
When slower growth (and/or better thickness control) is required, a process referred to as “atomic layer chemical vapor deposition” (ALCVD) or simply “atomic layer deposition” (ALD) is used. Also referred to at times as “atomic layer epitaxy” (ALE), this atomic-based process enables the deposition of alternating mono-layers of two elements onto a substrate (see, for example, U.S. Pat. No. 4,058,430). In this case, the achieved crystal lattice structure of the deposited film is thin, uniform and aligned with the structure of the substrate. In use, the reactants are brought to the substrate as alternating pulses, with “dead” time between the two different reactants. ALE makes use of the fact that the incoming material is strongly bound to the surface of the substrate until all of the sites available for chemisorptions are occupied. The dead time is used to flush an excess material from the reaction chamber. A main requirement of an atomic layer process is the use of a self-limiting chemical reaction as the means of achieving very accurate thickness control of the resulting film.
As the chemical reactants are alternately pulses, they will chemisorb onto the surface of the substrate to form the monolayer. Typically, one of the precursors will adsorb onto the substrate surface until it saturates the surface; further growth cannot occur until the second precursor is introduced. Therefore, the thickness of the film is controlled by the number of precursor cycles, rather than the deposition time (as is the case for conventional CVD processes). Cited limitations of atomic-based processes include slow growth rate, lack of selectivity (“selectivity” being the ability of film deposition only in areas defined by a mask) and limited film compositions (limited by the availability of suitable precursors).
Another variant of CVD is rapid thermal CVD (RTCVD), which takes advantage of rapid thermal processing to improve the efficiency of conventional CVD techniques. U.S. Pat. No. 5,002,630 describes an exemplary RTCVD process. During RTCVD, a semiconductor wafer is placed into a reaction chamber, which is thermally isolated from the wafer. The wafer is rapidly heated to a reaction temperature, which a reactant gas flowing over the wafer to induce reaction at the heated surface of the wafer. The wafer is then cooled and removed from the chamber, ready for further processing.
The RTCVD of single crystal silicon films on a silicon wafer is accomplished by using dichlorosilane as the source of silicon (carried by hydrogen). Hydrogen is mixed with argon or other inert gas. The process is carried out at temperatures of the silicon substrate above 750° C., and at a pressure no greater than atmospheric pressure. The single crystal silicon layer can be in-situ doped n-type or p-type to provide the required resistivity for the fabrication of integrated circuits.
Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor maintained under a reduced pressure (as described in, for example, U.S. Pat. No. 5,324,684). In this process, doping of a silicon substrate uses gas phase dopant sources that are maintained under reduced pressure. The silicon substrate is placed on a thermally isolated support structure in the chamber, allowing the temperature of the substrate to elevate via radiant heating. Once a defined, controlled temperature is reached, a gas phase source of the dopant is flowed across the substrate, where it is then absorbed. As with some other prior processes, an anneal step is used after dopant introduction.